Referring to FIG. 1 of the accompanying drawings, a complementary metal oxide semiconductor (CMOS) transistor comprises an n channel MOS (NMOS) and a p channel MOS (PMOS). Historically, a polycrystalline n+-Si gate is used as a gate electrode both in NMOS and PMOS transistors. For PMOS transistors additional boron implantation into the channel region of the Si substrate is needed to control the threshold voltage because of the low work function of n+-Si. This can produce short channel effects and large sub-threshold currents and thus the PMOS transistor is less scaleable than the NMOS transistor. In order to solve this problem, a dual gate configuration where polycrystalline n+-Si and p+-Si are used as the gate for the NMOS and PMOS transistors, respectively, has been suggested. However, the dual gate CMOS has drawbacks, most notably boron penetration (for PMOS) through the gate oxide and the poly-depletion effect. Instead of using a dual gate, a material with a work function close to the value of the middle of the bandgap of silicon (4.61 eV), can be used for both NMOS and PMOS transistors. A material with such a work function is called a mid-gap material and the process utilising this material for a gate electrode is known as mid-gap CMOS technology.
In addition, the contact surface of the gate electrode is actually provided by a silicide layer (TiSi2, CoSi2, PtSi2, PtSi or NiSi) on top of the polycrystalline Si gate (e.g. n+-Si) in current CMOS fabrication processes. At relatively high temperatures (e.g. 600° C.), the silicide film is usually degraded by two phenomena: inversion and agglomeration. Inversion is due to the grain growth of Si during the formation of silicide and occurs when the metal (e.g. Co, Ni) is the diffusing species during the growth of the silicide. This phenomenon results in suicide grains inside Si and at the interface between gate electrode and the silicon oxide layer on the Si wafer as well as large grains of Si at the surface, causing inversion. Agglomeration on the other hand is due to a reduction of the interfacial energy and results in large grains of silicide extended across the polycrystalline Si. These two phenomena limit the use of silicide as a good contact material for the gate electrode. A review of the problems caused by inversion and agglomeration can be found in Colgan EG, Gambino J P, Hong Q Z, MAT SCI ENG R 16 (1996) 43.
Several materials, such as Mo, MoSi2, W, WSi2, and TiN, have been proposed as mid-gap materials. However the use of these materials involves complex processing and has other drawbacks. Polycrystalline alloys of Si and Ge with silicide contacts have also been studied but do not alleviate the inversion and agglomeration problems. For the challenge presented in identifying suitable gate electrode materials, please refer to The International Technology Roadmap For Semiconductors: 1999.